SPEAR 3 BPM Development

last update: 22 Apr 2005

This web page contains documentation of hardware used in the SPEAR 3 BPM system. With time, it will also contain reports of developments made here on the system. This page and the information contained here is intended for the confidential use of the SSRL bpm development group.

Echotek documentation

The BPM analog IF is digitized and digitally down-converted on a board purchased from Echotek Corporation. The board is the ECDR-814. This site contains pdf versions of some of the relevant Echotek documentation.

There is some analog IF signal processing available on the ECDR-814. The IF can either be fed straight through to the digitizer , or it first passes through a gain block and a digital attenuator before the digitizer.

The digitizer output is the input to a programmable digital receiver chip, the AD6620 from Analog Devices. A later version of the manual, not on the Analog Devices web site as of March 2001, is also here.

The AD6620/external accumulator output is buffered by IDT72V36110 FIFOs.

The ECDR-814 interfaces with the VME bus by means of a chipset from Cypress Semiconductor. The programmable chip in this set is the CY7C961.

The ECDR814 is designed to transfer data using the Race++ protocol. Echotek makes a Race++ switch that can connect four boards.

Bergoz electronics

SSRL is purchasing modified versions of the standard MX-BPM module manufactured by Bergoz Instrumentation. The modules will be modified to allow periodic external control of the button selection, input of an external local oscillator, and output of an intermediate frequency for possible digitizing by our digital receiver.

Bergoz documentation

This site contains pdf versions of the schematics of the standard module.

Also posted on this site is an addendum to the standard users manual written by Julien Bergoz discussing and documenting the changes made for the SPEAR 3 model.

Bergoz hardware

SSRL has evaluated a slightly modified standard Bergoz MX-BPM module with the goal of characterizing its behavior for our application with the SSRL desired modifications of this module. A report detailing the results of this evaluation is presented here.

SSRL has proposed minor changes, detailed in a report sent to Bergoz, to the external control of the MX-BPM in order to allow the switches to be externally synchronized with the orbit feedback and orbit interlock timing systems. These changes will be incorporated into our electronics.

Other commercial hardware boards

The current CPU choice for the VME crate is the Synergy Microsystems SVGM5. The latest BSP for the SVGM5 supports Tornado 2.0 and VxWorks 5.4. Reference data containing specifics about the SPEAR BPM module hardware, connections of modules to electronic crates and chassis, etc., is located in the common NT directory structure at //ssrlhost1/Groups/Accel/Controls/bpm/documentation.

Hardware subsystems designed in house

We have designed several systems for our single turn BPM processor. This section contains results of tests we made to better choose our design.

RF Switches

The GaAsFET multiplexing switch we used in our SPEAR 2 design has a much greater than expected rise time to achieve the final few percent of its amplitude. Discussions with an engineer from Alpha Industries suggest that we might be able to improve the total (0%-100%) turn-on time of the switch by using a switch that allows us to directly drive the gate, and then tailoring the gate pulse for our application.

One possible alternate switch vendor is Hittite Microwave Corporation. They do not have a SP4T switch that meets our isolation specifications, but suggest that we could combine several SP2T switches to build what we want. They have a series of application notes, some of which are quite relevant to our project. One of these notes discusses issues relevant to the construction of such a compound switch.

Another possible switch vendor is Peregrine Semiconductor which makes a silicon on sapphire MOSFET switch. The Bergoz module uses a switch from Mini-Circuits.

We have tested switches from these three vendors in our application and have found that the tested switches from Peregrine and Hittite turn on to steady state values in a microsecond time scale while the Mini-Circuits switch has the same long time behavior as does the original Alpha switch that we used.

Digital Timing Board

The complete BPM system needs many digital signals, synchronized to the revolution frequency and each other, to control the data acquisition. Jeff Olsen is designing the timing crate driver as the VME module that will handle this synchronization.

Calibration Tone Combiner

We will build a processing system that will process the four buttons of a BPM module in parallel. In order to normalize out errors due to the variations in the four independent gain stages, we will inject an identical calibration tone into each of the four channels and measure its amplitude, using the second receiver chip in each channel on the Echotek module.

We solicited bids from manufacturers of passive microwave components to build a device that will inject the calibration signal. It will first split the tone four ways and then combine the individual tone signals with the four button signals. The details of our request are in an informational document on the front end coupler that we have sent to potential vendors.

Upon receipt of prototype versions of these combiners we conducted tests that led us to the choice for the production version. We present both the test results and the mechanical outline of the final coupler.

Discussions with other laboratories and vendors

We often hold discussions with our colleagues in other laboratories and commercial vendors working on BPM instrumentation. The results of these conversations are sometimes summarized and recorded here.

SSRL single turn BPM processor design

We designed our own single turn BPM processor electronics, incorporating the digital receiver technology to improve our processing speed and accuracy. We presented several conference papers on the concept, including a beam instrumentation workshop conference paper. Based on the results of bench testing of the ECDR814 and further refinements of our design criteria, we produced a design report for the RF/IF converter, the analog front end, of the processor. Echotek built this module to our design and has provided the module schematic and the backplane schematic.

Application notes

During the design process application notes are sometimes written to document certain decisions. Pdf versions of these documents are listed here, in no particular order.

Laboratory Documentation

The rack layout and the network connections of our laboratory in Building 6 are documented here.

All of the frequencies used in the operation of the bpm system are harmonically related. If these signals are generated from the system made by Wenzel Associates, only two signal sources are needed, one for the RF frequency and the other for the calibration tone. Before this equipment arrives, the signals need to be generated by multiple signal sources. In order to ease the effort of setting the frequencies, the "RF frequency" in the lab will be slightly higher than the actual 476.3 MHz used in SPEAR3. A table of test frequencies for use in the lab is documented here.

Software tools

The software running the BPM system is currently based on the RTEMS operating system, an open source, public domain system managed by On-Line Applications Research.

The solution that may fix the current software problem you are having with the ECDR814 board may be documented in this list of significant software changes

James J. Sebek